Embodiments of the disclosed technology relate to a manufacturing method of an array substrate.
TFT-LCDs have many advantages, such as small volume, low power consumption and non-radiation, and have dominated the current flat panel display market. A TFT-LCD is formed by bonding an array substrate and a color filter substrate. As shown in FIG. 1, a typical TFT-LCD array substrate mainly comprises: a base substrate (for example, glass substrate) 1, a gate electrode 2, a gate insulating layer 3 (SiNx) formed on the gate electrode 2, an active layer, a data line and source/drain (S/D) electrodes 6 on the active layer, a passivation layer (SiNx) 9 covering thereon, and a transparent pixel electrode (for example, ITO electrode) 7. For example, the active layer can be composed by a stack of an amorphous silicon thin film 4 (for example, a-Si:H) and an ohmic contact layer 5 (for example, n+ a-Si). A passivation layer via hole 8 is disposed in the passivation layer 9 above the drain electrode, and the ITO electrode 7 is connected with the drain electrode through the passivation layer via hole 8. In the prior art, a four-mask (4-mask) process is often used in the manufacturing the TFT-LCD array substrate. The specific steps of the method will be described hereinafter by referring to FIGS. 2(a) to 2(d).
(1) depositing a gate metal film on a glass substrate 1, and forming a gate signal line (not shown) and a gate electrode 2 by using a gate mask, as shown in FIG. 2(a);
(2) successively depositing a gate insulation layer 3, an amorphous silicon thin film 4, an ohmic contact layer 5 and a metal layer 6 on the glass substrate 1 after the step (1), and forming a photoresist pattern by an exposure through a grey tone mask and a development process, and removing the redundant parts of the active layer, the metal layer 6 and the photoresist through multiple etching processes so as to form a data line, source/drain electrodes 6, and a channel between the source and drain electrodes, as shown in FIG. 2(b);
(3) depositing a thin film for forming a passivation layer 9 on the substrate 1 after the step (2), and forming a passivation layer via hole 8 in a portion of the passivation layer which located above the drain electrode by performing a masking and etching process on the passivation layer 9, as shown in FIGS. 2(c); and
(4) depositing an ITO electrode layer on the substrate after the step (3), and forming a pixel electrode 7 by using an ITO mask, and the pixel electrode 7 is connected with the drain electrode through the passivation layer via hole 8, as shown in FIG. 2(d).
FIGS. 3-1(a) to 3-6(b) are schematic diagrams showing an etching effect of the above step (2) in the procedure of manufacturing the TFT-LCD array substrate by using the conventional 4-mask process, wherein FIGS. 3-1(a), 3-2(a), 3-3(a), 3-4(a), 3-5(a), and 3-6(a) are cross sectional views of a part corresponding to a data line and taken along a line A-A in FIG. 1, and FIGS. 3-1(b), 3-2(b), 3-3(b), 3-4(b), 3-5(b), and 3-6(b) are cross sectional views of a part corresponding to a thin film transistor (TFT) and taken along a line B-B in FIG. 1. In these figures, a stacking sequence from the bottom to the top of an amorphous silicon thin film 4, an ohmic contact layer 5, a metal layer 6, and a photoresist layer 10 is provided on a glass substrate 1. For convenience of illustration, the gate insulating layer is omitted in these figures.
The multiple etching processes in the step (2) are as follows in detail: firstly, removing most of the metal layer outside the pixel region by a first wet etching, as shown in FIGS. 3-2(a) and FIGS. 3-2(b); subsequently, removing most of the active layer outside the pixel region by an active layer etch (an etch for forming the pattern of the active layer), as shown in FIGS. 3-3(a) and 3-3(b); then thinning the photoresist by an ashing process so as to expose the metal layer within the channel region, as shown in FIGS. 3-4(a) and FIGS. 3-4(b); then performing a second wet etching process so as to remove the metal layer within the channel region, as shown in FIGS. 3-5(a) and 3-5(b); finally, etching a part of the active layer within the channel region by a N+ etching process. Thus, a data line, a channel and source/drain electrodes are formed, as shown in FIGS. 3-6(a) and 3-6(b). The multiple etching processes are also called as a SDT etching process.
The multiple etching processes are complex and needs a long period of time. Generally, a gas mixture of SF6 and O2, which has a relatively large etching rate on the photoresist but small etching rate on the active layer, is used to ash the photoresist. In addition, a gas mixture composed of SF6 and Cl2, which has a relatively large etching rate on the active layer but small etching rate on the photoresist, is used in etching the active layer. The gas mixture has a relatively higher etching rate on the gate insulation layer at the lower part, so that the gate insulation layer is etched so much and an uneven embossing mura is caused. This unevenness may have influence on the product quality after a module is formed. Furthermore, in the multiple etching process of the conventional 4-mask process, the active layer is etched for forming the active layer pattern before the photoresist is ashed for exposing the channel region, and thus a relatively large amount of active layer wing (also called active layer tail) is remained at the two sides of the data line and the two sides of the TFT region (including the source/drain regions and the channel region), as shown by “h1” in FIGS. 3-6(a) and 3-6(b). The active layer wing at the two sides of the data line and the two sides of the TFT region may exert influence on the design quality, thereby degrading the product quality.